Messages in this thread | | | From | Jerome Brunet <> | Subject | Re: [PATCH 1/4] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel | Date | Thu, 16 Apr 2020 12:32:21 +0200 |
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On Tue 14 Apr 2020 at 22:00, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not > easy to see that the vendor kernel does the same, but it actually does. > meson_clk_pll_ops in mainline still cannot fully recalculate all rates > from the HDMI PLL registers because some register bits (at the time of > writing it's unknown which bits are used for this) double the HDMI PLL > output rate (compared to simply considering M, N and FRAC).
Have you considered adding a fixed_factor pre-multiplier, like in the gxbb driver ?
Seems to be the same thing
> > Update the vid_pll_in_sel parent so our clock calculation works for > simple clock settings like the CVBS output (where no rate doubling is > going on). The PLL ops need to be fixed later on for more complex clock > settings (all HDMI rates). > > Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") > Suggested-by: Neil Armstrong <narmstrong@baylibre.com> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > drivers/clk/meson/meson8b.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index 7c55c695cbae..90d284ffc780 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -1077,7 +1077,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { > * Meson8m2: vid2_pll > */ > .parent_hws = (const struct clk_hw *[]) { > - &meson8b_hdmi_pll_dco.hw > + &meson8b_hdmi_pll_lvds_out.hw > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT,
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