Messages in this thread | | | Subject | Re: [PATCH v2 5/7] iommu/vt-d: Save prq descriptors in an internal list | From | Lu Baolu <> | Date | Fri, 17 Apr 2020 11:25:18 +0800 |
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Hi Kevin,
On 2020/4/16 9:46, Lu Baolu wrote: > On 2020/4/15 17:30, Tian, Kevin wrote: >>> From: Lu Baolu<baolu.lu@linux.intel.com> >>> Sent: Wednesday, April 15, 2020 1:26 PM >>> >>> Currently, the page request interrupt thread handles the page >>> requests in the queue in this way: >>> >>> - Clear PPR bit to ensure new interrupt could come in; >>> - Read and record the head and tail registers; >>> - Handle all descriptors between head and tail; >>> - Write tail to head register. >>> >>> This might cause some descriptors to be handles multiple times. >>> An example sequence: >>> >>> - Thread A got scheduled with PRQ_1 and PRQ_2 in the queue; >>> - Thread A clear the PPR bit and record the head and tail; >>> - A new PRQ_3 comes and Thread B gets scheduled; >>> - Thread B record the head and tail which includes PRQ_1 >>> and PRQ_2. >> I may overlook something but isn't the prq interrupt thread >> per iommu then why would two prq threads contend here? > > The prq interrupt could be masked by the PPR (Pending Page Request) bit > in Page Request Status Register. In the interrupt handling thread once > this bit is clear, new prq interrupts are allowed to be generated. > > So, if a page request is in process and the PPR bit is cleared, another > page request from any devices under the same iommu could trigger another > interrupt thread.
Rechecked the code. You are right. As long as the interrupt thread is per iommu, there will only single prq thread scheduled. I will change this accordingly in the new version. Thank you for pointing this out.
Best regards, baolu
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