Messages in this thread | | | Subject | Re: [PATCH 4/5] net: macb: WoL support for GEM type of Ethernet controller | From | Florian Fainelli <> | Date | Thu, 16 Apr 2020 12:25:24 -0700 |
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On 4/16/2020 10:44 AM, nicolas.ferre@microchip.com wrote: > From: Nicolas Ferre <nicolas.ferre@microchip.com> > > Adapt the Wake-on-Lan feature to the Cadence GEM Ethernet controller. > This controller has different register layout and cannot be handled by > previous code. > We disable completely interrupts on all the queues but the queue 0. > Handling of WoL interrupt is done in another interrupt handler > positioned depending on the controller version used, just between > suspend() and resume() calls. > It allows to lower pressure on the generic interrupt hot path by > removing the need to handle 2 tests for each IRQ: the first figuring out > the controller revision, the second for actually knowing if the WoL bit > is set. > > Queue management in suspend()/resume() functions inspired from RFC patch > by Harini Katakam <harinik@xilinx.com>, thanks! > > Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> > ---
[snip]
> > +static irqreturn_t gem_wol_interrupt(int irq, void *dev_id) > +{ > + struct macb_queue *queue = dev_id; > + struct macb *bp = queue->bp; > + u32 status; > + > + status = queue_readl(queue, ISR); > + > + if (unlikely(!status)) > + return IRQ_NONE; > + > + spin_lock(&bp->lock); > + > + if (status & GEM_BIT(WOL)) { > + queue_writel(queue, IDR, GEM_BIT(WOL)); > + gem_writel(bp, WOL, 0); > + netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n", > + (unsigned int)(queue - bp->queues), > + (unsigned long)status); > + if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) > + queue_writel(queue, ISR, GEM_BIT(WOL));
You would also need a pm_wakeup_event() call here to record that this device did wake-up the system. -- Florian
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