Messages in this thread | | | Subject | Re: [PATCH v1 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC | From | John Crispin <> | Date | Thu, 16 Apr 2020 15:51:32 +0200 |
| |
On 16.04.20 15:20, Arnd Bergmann wrote: > On Thu, Apr 16, 2020 at 2:40 PM Boris Brezillon > <boris.brezillon@collabora.com> wrote: >> On Thu, 16 Apr 2020 15:26:51 +0300 >> Andy Shevchenko <andy.shevchenko@gmail.com> wrote: >>> On Thu, Apr 16, 2020 at 3:03 PM Boris Brezillon >>> <boris.brezillon@collabora.com> wrote: >>>> On Thu, 16 Apr 2020 19:38:03 +0800 >>>> Note that the NAND subsystem is full of unmaintained legacy drivers, so >>>> every time we see someone who could help us get rid or update one of >>>> them we have to take this opportunity. >>> >>> Don't we rather insist to have a MAINTAINERS record for new code to >>> avoid (or delay at least) the fate of the legacy drivers? >>> >> >> Well, that's what we do for new drivers, but the xway driver has been >> added in 2012 and the policy was not enforced at that time. BTW, that >> goes for most of the legacy drivers in have in the NAND subsystems >> (some of them even predate the git era). >> >> To be clear, I just checked and there's no official maintainer for this >> driver. Best option would be to Cc the original author and contributors >> who proposed functional changes to the code, as well as the MIPS >> maintainers (Xway is a MIPS platform). > > A lot of the pre-acquisition code for lantiq was contributed by Hauke > Mehrtens and John Crispin. There was an intermediate generation of > MIPS SoCs with patches posted for review by Intel in 2018 (presumably > by the same organizatiob), but those were never resubmitted after v2 > and never merged: > > https://lore.kernel.org/linux-mips/20180803030237.3366-1-songjun.wu@linux.intel.com/ > > Arnd >
Hi,
the legacy Mips SoC had a External Bus Unit (EBU), similar to an Intel/Hitachi style bus. It was used back then for lots of things, sometimes driving Leds via 74* latches, Arcadyan used it for external reset lines and very rarely was it used for nand.
Looking at this series and comparing it with xway_nand.c we see that the init sequence is near identical. Best guess is that the mountain lion uses an internal block very similar to what the legacy mips silicon used just in a newer generation and the new proposed driver is more feature complete.
If this is the case ideally the xway_nand.c is dropped and that silicon is made working with the newer driver. Chances are that we just need to add a "support less features" style flag.
Unfortunately i no longer have the evalkit for the Mips SoCs.
John
| |