Messages in this thread | | | Subject | Re: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register | From | Anshuman Khandual <> | Date | Mon, 13 Apr 2020 09:05:28 +0530 |
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On 04/09/2020 06:25 PM, Will Deacon wrote: > On Tue, Jan 28, 2020 at 06:09:05PM +0530, Anshuman Khandual wrote: >> Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487E.a >> specification. Except RAS and AMU, all other feature bits are now enabled. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/sysreg.h | 3 +++ >> arch/arm64/kernel/cpufeature.c | 2 ++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 054aab7ebf1b..469d61c8fabf 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -718,6 +718,9 @@ >> #define ID_ISAR6_DP_SHIFT 4 >> #define ID_ISAR6_JSCVT_SHIFT 0 >> >> +#define ID_PFR0_DIT_SHIFT 24 >> +#define ID_PFR0_CSV2_SHIFT 16 >> + >> #define ID_PFR2_SSBS_SHIFT 4 >> #define ID_PFR2_CSV3_SHIFT 0 >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index c1e837fc8f97..9e4dab15c608 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -341,6 +341,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = { >> }; >> >> static const struct arm64_ftr_bits ftr_id_pfr0[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), > > Same comment as CSV3 here. Why is CSV2 being treated as strict here, but not > in the aa64* register?
Sure, will change.
> > Will >
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