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    Subject[RFC PATCH v5 2/8] arm64: Add level-hinted TLB invalidation helper
    Date
    From: Marc Zyngier <maz@kernel.org>

    Add a level-hinted TLB invalidation helper that only gets used if
    ARMv8.4-TTL gets detected.

    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
    ---
    arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++
    1 file changed, 30 insertions(+)

    diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
    index bc3949064725..5f9f189bc6d2 100644
    --- a/arch/arm64/include/asm/tlbflush.h
    +++ b/arch/arm64/include/asm/tlbflush.h
    @@ -10,6 +10,7 @@

    #ifndef __ASSEMBLY__

    +#include <linux/bitfield.h>
    #include <linux/mm_types.h>
    #include <linux/sched.h>
    #include <asm/cputype.h>
    @@ -59,6 +60,35 @@
    __ta; \
    })

    +#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
    +
    +#define __tlbi_level(op, addr, level) \
    + do { \
    + u64 arg = addr; \
    + \
    + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
    + level) { \
    + u64 ttl = level; \
    + \
    + switch (PAGE_SIZE) { \
    + case SZ_4K: \
    + ttl |= 1 << 2; \
    + break; \
    + case SZ_16K: \
    + ttl |= 2 << 2; \
    + break; \
    + case SZ_64K: \
    + ttl |= 3 << 2; \
    + break; \
    + } \
    + \
    + arg &= ~TLBI_TTL_MASK; \
    + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
    + } \
    + \
    + __tlbi(op, arg); \
    + } while (0)
    +
    /*
    * TLB Invalidation
    * ================
    --
    2.19.1

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