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    Subject[PATCH 5.5 114/176] MIPS: cavium_octeon: Fix syncw generation.
    Date
    From: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

    commit 97e914b7de3c943011779b979b8093fdc0d85722 upstream.

    The Cavium Octeon CPU uses a special sync instruction for implementing
    wmb, and due to a CPU bug, the instruction must appear twice. A macro
    had been defined to hide this:

    #define __SYNC_rpt(type) (1 + (type == __SYNC_wmb))

    which was intended to evaluate to 2 for __SYNC_wmb, and 1 for any other
    type of sync. However, this expression is evaluated by the assembler,
    and not the compiler, and the result of '==' in the assembler is 0 or
    -1, not 0 or 1 as it is in C. The net result was wmb() producing no code
    at all. The simple fix in this patch is to change the '+' to '-'.

    Fixes: bf92927251b3 ("MIPS: barrier: Add __SYNC() infrastructure")
    Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
    Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
    Signed-off-by: Paul Burton <paulburton@kernel.org>
    Cc: linux-mips@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/mips/include/asm/sync.h | 4 +++-
    1 file changed, 3 insertions(+), 1 deletion(-)

    --- a/arch/mips/include/asm/sync.h
    +++ b/arch/mips/include/asm/sync.h
    @@ -155,9 +155,11 @@
    * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use
    * optimized memory barrier primitives."). Here we specify that the affected
    * sync instructions should be emitted twice.
    + * Note that this expression is evaluated by the assembler (not the compiler),
    + * and that the assembler evaluates '==' as 0 or -1, not 0 or 1.
    */
    #ifdef CONFIG_CPU_CAVIUM_OCTEON
    -# define __SYNC_rpt(type) (1 + (type == __SYNC_wmb))
    +# define __SYNC_rpt(type) (1 - (type == __SYNC_wmb))
    #else
    # define __SYNC_rpt(type) 1
    #endif

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