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    Subject[PATCH v2 01/22] dt-bindings: memory: tegra20: mc: Document new interconnect property
    Date
    Memory controller is interconnected with memory clients and with the
    external memory controller. Document new interconnect property which
    turns memory controller into interconnect provider.

    Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
    ---
    .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++
    1 file changed, 3 insertions(+)

    diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
    index e55328237df4..739b7c6f2e26 100644
    --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
    +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
    @@ -16,6 +16,8 @@ Required properties:
    IOMMU specifier needed to encode an address. GART supports only a single
    address space that is shared by all devices, therefore no additional
    information needed for the address encoding.
    +- #interconnect-cells : Should be 1. This cell represents memory client.
    + The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.

    Example:
    mc: memory-controller@7000f000 {
    @@ -27,6 +29,7 @@ Example:
    interrupts = <GIC_SPI 77 0x04>;
    #reset-cells = <1>;
    #iommu-cells = <0>;
    + #interconnect-cells = <1>;
    };

    video-codec@6001a000 {
    --
    2.25.1
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