Messages in this thread | | | Date | Thu, 26 Mar 2020 14:51:47 +0000 | From | Marc Zyngier <> | Subject | Re: [PATCH v5 1/6] dt-bindings: pci: Update iProc PCI binding for INTx support |
| |
Srinath,
Please note that Andrew's email address as changed (see the MAINTAINERS file).
On 2020-03-26 06:48, Srinath Mannam wrote: > From: Ray Jui <ray.jui@broadcom.com> > > Update the iProc PCIe binding document for better modeling of the > legacy > interrupt (INTx) support. > > Signed-off-by: Ray Jui <ray.jui@broadcom.com> > Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 48 > ++++++++++++++++++---- > 1 file changed, 41 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > index df065aa..d3f833a 100644 > --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > @@ -13,9 +13,6 @@ controller, used in Stingray > PAXB-based root complex is used for external endpoint devices. > PAXC-based > root complex is connected to emulated endpoint devices internal to the > ASIC > - reg: base address and length of the PCIe controller I/O register > space > -- #interrupt-cells: set to <1> > -- interrupt-map-mask and interrupt-map, standard PCI properties to > define the > - mapping of the PCIe interface to interrupt numbers > - linux,pci-domain: PCI domain ID. Should be unique for each host > controller > - bus-range: PCI bus numbers covered > - #address-cells: set to <3> > @@ -41,6 +38,21 @@ Required: > - brcm,pcie-ob-axi-offset: The offset from the AXI address to the > internal > address used by the iProc PCIe core (not the PCIe address) > > +Legacy interrupt (INTx) support (optional): > + > +Note INTx is for PAXB only. > +- interrupt-map-mask and interrupt-map, standard PCI properties to > define > +the mapping of the PCIe interface to interrupt numbers > + > +In addition, a sub-node that describes the legacy interrupt controller > built > +into the PCIe controller. > +This sub-node must have the following properties: > + - compatible: must be "brcm,iproc-intc" > + - interrupt-controller: claims itself as an interrupt controller for > INTx > + - #interrupt-cells: set to <1> > + - interrupts: interrupt line wired to the generic GIC for INTx > support > + - interrupt-parent: Phandle to the parent interrupt controller > + > MSI support (optional): > > For older platforms without MSI integrated in the GIC, iProc PCIe core > provides > @@ -77,8 +89,11 @@ Example: > reg = <0x18012000 0x1000>; > > #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie0_intc 0>, > + <0 0 0 2 &pcie0_intc 1>, > + <0 0 0 3 &pcie0_intc 2>, > + <0 0 0 4 &pcie0_intc 3>; > > linux,pci-domain = <0>; > > @@ -98,6 +113,14 @@ Example: > > msi-parent = <&msi0>; > > + pcie0_intc: interrupt-controller { > + compatible = "brcm,iproc-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
There is no such thing as IRQ_TYPE_NONE in the GIC binding. Please update this to the right trigger type (which better be level high...)
M. -- Jazz is not dead. It just smells funny...
| |