Messages in this thread Patch in this message | | | From | Jolly Shah <> | Subject | [PATCH v2 1/4] drivers: clk: zynqmp: Limit bestdiv with maxdiv | Date | Mon, 2 Mar 2020 13:50:40 -0800 |
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From: Rajan Vaja <rajan.vaja@xilinx.com>
Clock divider value should not be greater than maximum divider value. So use minimum of best divider or maximum divider value.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> --- drivers/clk/zynqmp/divider.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 973cdf0..7d2cb61 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -198,6 +198,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) bestdiv = rate % *prate ? 1 : bestdiv; + + bestdiv = min_t(u32, bestdiv, divider->max_div); *prate = rate * bestdiv; return rate; -- 2.7.4
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