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    Subject[PATCH 5.5 113/189] drm/amd/powerplay: fix pre-check condition for setting clock range
    Date
    From: Prike Liang <Prike.Liang@amd.com>

    commit 80381d40c9bf5218db06a7d7246c5478c95987ee upstream.

    This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
    dpm clock layout and a zero frequency dpm level as following case.

    cat pp_dpm_mclk
    0: 1200Mhz
    1: 1200Mhz
    2: 800Mhz
    3: 0Mhz

    Signed-off-by: Prike Liang <Prike.Liang@amd.com>
    Reviewed-by: Evan Quan <evan.quan@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
    drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 ---
    2 files changed, 1 insertion(+), 4 deletions(-)

    --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
    +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
    @@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_c
    {
    int ret = 0;

    - if (min <= 0 && max <= 0)
    + if (min < 0 && max < 0)
    return -EINVAL;

    if (!smu_clk_dpm_is_enabled(smu, clk_type))
    --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
    +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
    @@ -373,9 +373,6 @@ int smu_v12_0_set_soft_freq_limited_rang
    {
    int ret = 0;

    - if (max < min)
    - return -EINVAL;
    -
    switch (clk_type) {
    case SMU_GFXCLK:
    case SMU_SCLK:

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