Messages in this thread | | | Subject | Re: [PATCH v2 3/9] ASoC: tegra: add Tegra210 based DMIC driver | From | Sameer Pujar <> | Date | Fri, 7 Feb 2020 16:36:24 +0530 |
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On 2/6/2020 10:23 PM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 30.01.2020 13:33, Sameer Pujar пишет: > ... >> +static const struct reg_default tegra210_dmic_reg_defaults[] = { >> + { TEGRA210_DMIC_TX_INT_MASK, 0x00000001}, >> + { TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700}, >> + { TEGRA210_DMIC_CG, 0x1}, >> + { TEGRA210_DMIC_CTRL, 0x00000301}, >> + /* Below enables all filters - DCR, LP and SC */ >> + { TEGRA210_DMIC_DBG_CTRL, 0xe }, >> + /* Below as per latest POR value */ >> + { TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0x0}, >> + /* LP filter is configured for pass through and used to apply gain */ >> + { TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000}, >> + { TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000}, >> + { TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x0}, >> + { TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x0}, >> +}; > I'd add a space on the right side of `}`, for consistency with the left.
Do you mean like this? { TEGRA210_DMIC_TX_INT_MASK, 0x00000001 }, { TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700 }, . . .
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