Messages in this thread | | | Date | Fri, 7 Feb 2020 10:45:34 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH V2] perf/x86: Add Intel Tiger Lake uncore support |
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On Thu, Feb 06, 2020 at 08:15:27AM -0800, kan.liang@linux.intel.com wrote: > From: Kan Liang <kan.liang@linux.intel.com> > > For MSR type of uncore units, there is no difference between Ice Lake > and Tiger Lake. Share the same code with Ice Lake. > > Tiger Lake has two MCs. Both of them are located at 0:0:0. The BAR > offset is still 0x48. The offset of the two MCs is 0x10000. > Each MC has three counters to count every read/write/total issued by the > Memory Controller to DRAM. The counters can be accessed by MMIO. > They are free-running counters. > > The offset of counters are different for TIGERLAKE_L and TIGERLAKE. > Add separated mmio_init() functions. > > Reviewed-by: Andi Kleen <ak@linux.intel.com> > Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Thanks!
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