Messages in this thread | | | Subject | Re: [PATCH v3 3/8] x86/split_lock: Cache the value of MSR_TEST_CTRL in percpu data | From | Xiaoyao Li <> | Date | Fri, 7 Feb 2020 12:18:44 +0800 |
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On 2/7/2020 4:23 AM, Arvind Sankar wrote: > On Thu, Feb 06, 2020 at 03:04:07PM +0800, Xiaoyao Li wrote: >> Cache the value of MSR_TEST_CTRL in percpu data msr_test_ctrl_cache, >> which will be used by KVM module. >> >> It also avoids an expensive RDMSR instruction if SLD needs to be context >> switched. >> >> Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com> >> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> >> --- >> arch/x86/include/asm/cpu.h | 2 ++ >> arch/x86/kernel/cpu/intel.c | 19 ++++++++++++------- >> 2 files changed, 14 insertions(+), 7 deletions(-) >> >> diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h >> index ff567afa6ee1..2b20829db450 100644 >> --- a/arch/x86/include/asm/cpu.h >> +++ b/arch/x86/include/asm/cpu.h >> @@ -27,6 +27,8 @@ struct x86_cpu { >> }; >> >> #ifdef CONFIG_HOTPLUG_CPU >> +DECLARE_PER_CPU(u64, msr_test_ctrl_cache); >> + > > Why does this depend on HOTPLUG_CPU? >
Sorry, my bad,
It should be under CONFIG_CPU_SUP_INTEL
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