Messages in this thread | | | Date | Mon, 07 Dec 2020 18:53:43 +0100 | From | Stefan Agner <> | Subject | Re: [PATCH v2 3/5] ARM: dts: meson: fix PHY deassert timing requirements |
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On 2020-12-05 14:04, Martin Blumenstingl wrote: > Hi Stefan, > > On Tue, Dec 1, 2020 at 2:21 PM Stefan Agner <stefan@agner.ch> wrote: >> >> According to the datasheet (Rev. 1.9) the RTL8211F requires at least >> 72ms "for internal circuits settling time" before accessing the PHY >> egisters. On similar boards with the same PHY this fixes an issue where > there's a typo here: it should be "registers" > this is the same for the other four patches also
Whoops, will send v3 shortly.
> >> Ethernet link would not come up when using ip link set down/up. > I have never experienced that myself but gotten a few reports about this. > thank you very much for coming up with info from the datasheet! > > the following stmmac patch [0] has been added recently which may - or > may not - have any impact also.
Thanks for the hint, wasn't aware of that.
-- Stefan
> >> Fixes: a2c6e82e5341 ("ARM: dts: meson: switch to the generic Ethernet PHY reset bindings") >> Signed-off-by: Stefan Agner <stefan@agner.ch> > with above typo fixed: > Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > and also: > Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # > on Odroid-C1+ > > > Best regards, > Martin > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/net/ethernet/stmicro/stmmac?id=56311a315da7ebc668dbcc2f1c99689cc10796c4
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