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    Subject[PATCH 5.10 283/717] powerpc/perf: Update the PMU group constraints for l2l3 events in power10
    Date
    From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>

    [ Upstream commit e924be7b0b0d1f37d0509c854a92c7a71e3cdfe7 ]

    In Power9, L2/L3 bus events are always available as a
    "bank" of 4 events. To obtain the counts for any of the
    l2/l3 bus events in a given bank, the user will have to
    program PMC4 with corresponding l2/l3 bus event for that
    bank.

    Commit 59029136d750 ("powerpc/perf: Add constraints for power9 l2/l3 bus events")
    enforced this rule in Power9. But this is not valid for
    Power10, since in Power10 Monitor Mode Control Register2
    (MMCR2) has bits to configure l2/l3 event bits. Hence remove
    this PMC4 constraint check from power10.

    Since the l2/l3 bits in MMCR2 are not per-pmc, patch handles
    group constrints checks for l2/l3 bits in MMCR2.

    Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
    Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/1606409684-1589-3-git-send-email-atrajeev@linux.vnet.ibm.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/powerpc/perf/isa207-common.c | 8 +++++---
    1 file changed, 5 insertions(+), 3 deletions(-)

    diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
    index f57f54f92c10f..38ed450c78557 100644
    --- a/arch/powerpc/perf/isa207-common.c
    +++ b/arch/powerpc/perf/isa207-common.c
    @@ -311,9 +311,11 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
    }

    if (unit >= 6 && unit <= 9) {
    - if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
    - mask |= CNST_L2L3_GROUP_MASK;
    - value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
    + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
    + if (unit == 6) {
    + mask |= CNST_L2L3_GROUP_MASK;
    + value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
    + }
    } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
    mask |= CNST_CACHE_GROUP_MASK;
    value |= CNST_CACHE_GROUP_VAL(event & 0xff);
    --
    2.27.0


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