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    Subject[PATCH 5.10 568/717] perf/x86/intel/lbr: Fix the return type of get_lbr_cycles()
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    commit f8129cd958b395575e5543ce25a8434874b04d3a upstream.

    The cycle count of a timed LBR is always 1 in perf record -D.

    The cycle count is stored in the first 16 bits of the IA32_LBR_x_INFO
    register, but the get_lbr_cycles() return Boolean type.

    Use u16 to replace the Boolean type.

    Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
    Reported-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: stable@vger.kernel.org
    Link: https://lkml.kernel.org/r/20201125213720.15692-2-kan.liang@linux.intel.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/events/intel/lbr.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/arch/x86/events/intel/lbr.c
    +++ b/arch/x86/events/intel/lbr.c
    @@ -919,7 +919,7 @@ static __always_inline bool get_lbr_pred
    return !(info & LBR_INFO_MISPRED);
    }

    -static __always_inline bool get_lbr_cycles(u64 info)
    +static __always_inline u16 get_lbr_cycles(u64 info)
    {
    if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
    !(x86_pmu.lbr_timed_lbr && info & LBR_INFO_CYC_CNT_VALID))

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