Messages in this thread | | | Subject | Re: [PATCH 4/8] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU | From | Samuel Holland <> | Date | Wed, 2 Dec 2020 20:44:29 -0600 |
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On 12/2/20 12:20 PM, Jernej Škrabec wrote: >> +}; >> + >> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { >> + .hws = { >> + [CLK_R_AHB] = &r_ahb_clk.hw, >> + [CLK_R_APB1] = &r_apb1_clk.common.hw, >> + [CLK_R_APB2] = &r_apb2_clk.common.hw, >> + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, > > Do we know if TWD exists? I tested I2C and IR. What is your source for these > clocks?
Looking at https://github.com/orangepi-xunlong/linux-orangepi and comparing drivers/clk/sunxi/clk-sun50iw[69].h, I see:
/* PRCM Register List */ #define CPUS_CFG 0x0000 #define CPUS_APBS1_CFG 0x000C #define CPUS_APBS2_CFG 0x0010 -#define CPUS_TIMER_GATE 0x011C #define CPUS_TWDOG_GATE 0x012C -#define CPUS_PWM_GATE 0x013C -#define CPUS_UART_GATE 0x018C #define CPUS_TWI_GATE 0x019C #define CPUS_RSB_GATE 0x01BC #define CPUS_CIR_CFG 0x01C0 #define CPUS_CIR_GATE 0x01CC #define CPUS_OWC_CFG 0x01E0 #define CPUS_OWC_GATE 0x01EC #define CPUS_RTC_GATE 0x020C #define CPUS_CLK_MAX_REG 0x020C
which suggests that TWD is still there, along with OWC/W1 and an undocumented RSB controller like the one in H6. Jernej, can you check RSB? It should be PL0/PL1 function 2 and MMIO base 0x7083000.
Cheers, Samuel
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