Messages in this thread | | | Subject | Re: [PATCH v2 00/13] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers | From | Stephen Boyd <> | Date | Thu, 17 Dec 2020 01:17:10 -0800 |
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Quoting Weiyi Lu (2020-11-08 18:13:15) > This series is based on v5.10-rc1 and > [v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1] in Mediatek MT8192 clock support series > > [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1604887429-29445-8-git-send-email-weiyi.lu@mediatek.com/ > > change since v1: > - add patch for MT8167
The last patch doesn't apply. Also the whole series is base64 encoded and confuses my MUA. Please resend.
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