Messages in this thread | | | Date | Tue, 15 Dec 2020 10:03:43 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v3 1/9] dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM |
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On Fri, 11 Dec 2020 13:15:55 -0800, Sowjanya Komatineni wrote: > Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled > when using DDR interface mode. > > This patch adds clock ID for this to dt-binding. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > include/dt-bindings/clock/tegra210-car.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >
Acked-by: Rob Herring <robh@kernel.org>
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