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SubjectRe: [PATCH v3 3/3] pinctrl: qcom: Clear possible pending irq when remuxing GPIOs
Hi,

On Thu, Dec 10, 2020 at 1:56 PM Stephen Boyd <swboyd@chromium.org> wrote:
>
> Quoting Douglas Anderson (2020-12-09 16:41:03)
> > Conceptually, we can envision the input on Qualcomm SoCs to pass
> > through a bunch of blocks between coming into the chip and becoming a
> > GPIO interrupt. From guessing and running a handful of tests, I
> > believe that we can represent the state of the world with a drawing
> > that looks something like this:
> >
> > +-----------------+ +-----------------+ +-----------------+
> > | INPUT | --> | PINMUX | | IS_INPUT |
> > +-----------------+ | | --> | |
> > | output bogus (?)| | output bogus (?)|
> > | if not muxed | | if input disab. |
> > +-----------------+ +-----------------+
> > |
> > +---------------------------------------------------+--> to PDC
> > |
> > V
> > +-----------------+ +-----------------+ +-----------------+
> > | INTR RAW ENABLE | | DETECTION LOGIC | | STATUS REGISTER |
> > | | | | | |
> > | output bogus (?)| --> | maybe handles | | latches inputs |
> > | if disabled | | polarity diffs | --> | that are high |
> > +-----------------+ | | | |
> > | maybe debounces | | write 1 to clr |
> > | level irqs | +-----------------+
> > +-----------------+ |
> > |
> > +---------------------------------------------------+
> > |
> > V
> > +-----------------+
> > | ENABLE |
> > | | +-----------------+
> > | nothing passes | --> | SUMMARY IRQ |
> > | through if | +-----------------+
> > | disabled |
> > +-----------------+
>
> This diagram doesn't make sense to me.

I've gutted most of this code for v4 after Maulik pointed out why my
testing was flawed. Hopefully v4 looks saner...

-Doug

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