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SubjectRe: [PATCH v3 3/9] clk: qoriq: provide constants for the type
Am 2020-11-09 23:05, schrieb Rob Herring:
> On Sun, Nov 08, 2020 at 07:51:07PM +0100, Michael Walle wrote:
>> To avoid future mistakes in the device tree for the clockgen module,
>> add
>> constants for the clockgen subtype as well as a macro for the PLL
>> divider.
>>
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>> Changes since v2:
>> - new patch
>>
>> drivers/clk/clk-qoriq.c | 13 +++++++------
>> include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
>> 2 files changed, 22 insertions(+), 6 deletions(-)
>> create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
>>
>> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
>> index 46101c6a20f2..70aa521e7e7f 100644
>> --- a/drivers/clk/clk-qoriq.c
>> +++ b/drivers/clk/clk-qoriq.c
>> @@ -7,6 +7,7 @@
>>
>> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>>
>> +#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
>> #include <linux/clk.h>
>> #include <linux/clk-provider.h>
>> #include <linux/clkdev.h>
>> @@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct
>> of_phandle_args *clkspec, void *data)
>> idx = clkspec->args[1];
>>
>> switch (type) {
>> - case 0:
>> + case QORIQ_CLK_SYSCLK:
>> if (idx != 0)
>> goto bad_args;
>> clk = cg->sysclk;
>> break;
>> - case 1:
>> + case QORIQ_CLK_CMUX:
>> if (idx >= ARRAY_SIZE(cg->cmux))
>> goto bad_args;
>> clk = cg->cmux[idx];
>> break;
>> - case 2:
>> + case QORIQ_CLK_HWACCEL:
>> if (idx >= ARRAY_SIZE(cg->hwaccel))
>> goto bad_args;
>> clk = cg->hwaccel[idx];
>> break;
>> - case 3:
>> + case QORIQ_CLK_FMAN:
>> if (idx >= ARRAY_SIZE(cg->fman))
>> goto bad_args;
>> clk = cg->fman[idx];
>> break;
>> - case 4:
>> + case QORIQ_CLK_PLATFORM_PLL:
>> pll = &cg->pll[PLATFORM_PLL];
>> if (idx >= ARRAY_SIZE(pll->div))
>> goto bad_args;
>> clk = pll->div[idx].clk;
>> break;
>> - case 5:
>> + case QORIQ_CLK_CORECLK:
>> if (idx != 0)
>> goto bad_args;
>> clk = cg->coreclk;
>> diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h
>> b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
>> new file mode 100644
>> index 000000000000..ddec7d0bdc7f
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +
>> +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
>> +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
>> +
>> +#define QORIQ_CLK_SYSCLK 0
>> +#define QORIQ_CLK_CMUX 1
>> +#define QORIQ_CLK_HWACCEL 2
>> +#define QORIQ_CLK_FMAN 3
>> +#define QORIQ_CLK_PLATFORM_PLL 4
>> +#define QORIQ_CLK_CORECLK 5
>> +
>> +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
>
> This is not used and doesn't seem like part of the ABI (shared with dts
> files).

TBH I haven't found a nice way to integrate this macro into the clock
driver. It is used in the device tree for the type PLATFORM_PLL.
Previously, you had "<&clockgen 4 1>", where 4 is the PLATFORM_PLL and 1
is actually "div-by-2". Thus I replaced it by <&clockgen
QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>. (I just realized that
QORIQ_CLK_PLL_DIV_BY(2) might be a better name.)

I already figured, that this might be a problem, if that macro isn't
used in the driver.

-michael

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