Messages in this thread Patch in this message | | | From | John Garry <> | Subject | [PATCH RFC v5 05/13] perf vendor events arm64: Add Architected events smmuv3-pmcg.json | Date | Fri, 6 Nov 2020 20:35:45 +0800 |
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Add JSON for Architected events from [0], Section 10.3 .
[0] https://static.docs.arm.com/ihi0070/a/IHI_0070A_SMMUv3.pdf
Signed-off-by: John Garry <john.garry@huawei.com> --- .../pmu-events/arch/arm64/smmuv3-pmcg.json | 58 +++++++++++++++++++ tools/perf/pmu-events/jevents.c | 2 + 2 files changed, 60 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json
diff --git a/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json b/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json new file mode 100644 index 000000000000..8a59ce48bf06 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json @@ -0,0 +1,58 @@ +[ + { + "PublicDescription": "Clock cycles", + "EventCode": "0x00", + "EventName": "smmuv3_pmcg.CYCLES", + "BriefDescription": "Clock cycles" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Transaction", + "EventCode": "0x01", + "EventName": "smmuv3_pmcg.TRANSACTION", + "BriefDescription": "Transaction" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "TLB miss caused by incoming transaction or (ATS or non-ATS) translation request", + "EventCode": "0x02", + "EventName": "smmuv3_pmcg.TLB_MISS", + "BriefDescription": "TLB miss caused by incoming transaction or (ATS or non-ATS) translation request" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Configuration cache miss caused by transaction or(ATS or non-ATS)translation request", + "EventCode": "0x03", + "EventName": "smmuv3_pmcg.CONFIG_CACHE_MISS", + "BriefDescription": "Configuration cache miss caused by transaction or(ATS or non-ATS)translation request" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Translation table walk access", + "EventCode": "0x04", + "EventName": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS", + "BriefDescription": "Translation table walk access" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Configuration structure access", + "EventCode": "0x05", + "EventName": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS", + "BriefDescription": "Configuration structure access" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "PCIe ATS Translation Request received", + "EventCode": "0x06", + "EventName": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ", + "BriefDescription": "PCIe ATS Translation Request received" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "PCIe ATS Translated Transaction passed through SMMU", + "EventCode": "0x07", + "EventName": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED", + "BriefDescription": "PCIe ATS Translated Transaction passed through SMMU" + "Unit": "smmuv3_pmcg", + } +] diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 7a65fd2d25bb..46e5253b0862 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -281,6 +281,8 @@ static struct map { { "hisi_sccl,ddrc", "hisi_sccl,ddrc" }, { "hisi_sccl,hha", "hisi_sccl,hha" }, { "hisi_sccl,l3c", "hisi_sccl,l3c" }, + /* it's not realistic to keep adding these, we need something more scalable ... */ + { "smmuv3_pmcg", "smmuv3_pmcg" }, { "L3PMC", "amd_l3" }, { "DFPMC", "amd_df" }, {} -- 2.26.2
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