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Subject[PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
Date
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Changes in v2:
- Changes as per Rob Herring's request on v1
---
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35 ++++++++++++++++++++--
1 file changed, 32 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index efc0198..749265c 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -27,6 +27,7 @@ select:
items:
- enum:
- sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache

required:
- compatible
@@ -34,7 +35,9 @@ select:
properties:
compatible:
items:
- - const: sifive,fu540-c000-ccache
+ - enum:
+ - sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
- const: cache

cache-block-size:
@@ -53,9 +56,15 @@ properties:

interrupts:
description: |
- Must contain entries for DirError, DataError and DataFail signals.
+ Must contain 3 entries for FU540 (DirError, DataError and DataFail) or 4
+ entries for other chips (DirError, DirFail, DataError, DataFail signals)
minItems: 3
- maxItems: 3
+ maxItems: 4
+ items:
+ - description: DirError interrupt
+ - description: DirFail interrupt
+ - description: DataError interrupt
+ - description: DataFail interrupt

reg:
maxItems: 1
@@ -67,6 +76,26 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.

+if:
+ properties:
+ compatible:
+ contains:
+ const: sifive,fu540-c000-ccache
+
+then:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DataError and DataFail signals.
+ maxItems: 3
+
+else:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DirFail, DataError, DataFail signals.
+ minItems: 4
+
additionalProperties: false

required:
--
2.7.4
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