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SubjectRe: [PATCH v5 3/4] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller
On Thu, Nov 19, 2020 at 08:01:28PM +0000, Dongjiu Geng wrote:
> The Hiedma Controller v310 Provides eight DMA channels, each
> channel can be configured for one-way transfer. The data can
> be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
> documentation describes DT bindings of this controller.
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> ---
> .../bindings/dma/hisilicon,hiedmacv310.yaml | 103 ++++++++++++++++++
> 1 file changed, 103 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
> new file mode 100644
> index 000000000000..fe5c5af4d3e1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/hisilicon,hiedmacv310.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HiSilicon Hiedma Controller v310 Device Tree Bindings
> +
> +description: |
> + These bindings describe the DMA engine included in the HiSilicon Hiedma
> + Controller v310 Device.
> +
> +maintainers:
> + - Dongjiu Geng <gengdongjiu@huawei.com>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + "#dma-cells":
> + const: 2
> +
> + "#clock-cells":
> + const: 2
The DMA controller is a clock provider? Odd. What does each cell
represent?

> +
> + compatible:
> + const: hisilicon,hiedmacv310
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + misc_regmap:
> + description: phandle pointing to the misc controller provider node.
> +
> + misc_ctrl_base:
> + maxItems: 1

These 2 can be a single property with phandle + reg offset.

Also, needs a vendor prefix and don't use '_'.

> +
> + clocks:
> + items:
> + - description: apb clock
> + - description: axi clock
> +
> + clock-names:
> + items:
> + - const: apb_pclk
> + - const: axi_aclk
> +
> + resets:
> + description: phandle pointing to the dma reset controller provider node.
> +
> + reset-names:
> + items:
> + - const: dma-reset
> +
> + dma-requests:
> + maximum: 32
> +
> + dma-channels:
> + maximum: 8
> +
> +
> +required:
> + - "#dma-cells"
> + - "#clock-cells"
> + - compatible
> + - misc_regmap
> + - misc_ctrl_base
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - dma-requests
> + - dma-channels
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/hi3559av100-clock.h>
> +
> + dma: dma-controller@10040000 {
> + compatible = "hisilicon,hiedmacv310";
> + reg = <0x10040000 0x1000>;
> + misc_regmap = <&misc_ctrl>;
> + misc_ctrl_base = <0x144>;
> + interrupts = <0 82 4>;
> + clocks = <&clock HI3559AV100_EDMAC1_CLK>, <&clock HI3559AV100_EDMAC1_AXICLK>;
> + clock-names = "apb_pclk", "axi_aclk";
> + #clock-cells = <2>;
> + resets = <&clock 0x16c 7>;
> + reset-names = "dma-reset";
> + dma-requests = <32>;
> + dma-channels = <8>;
> + #dma-cells = <2>;
> + };
> +
> +...
> --
> 2.17.1
>

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