Messages in this thread | | | From | Bin Meng <> | Date | Tue, 3 Nov 2020 18:00:25 +0800 | Subject | Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board |
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On Fri, Oct 30, 2020 at 5:08 PM Anup Patel <anup@brainfault.org> wrote: > > On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote: > > > > Add initial DTS for Microchip ICICLE board having only > > essential devcies (clocks, sdhci, ethernet, serial, etc). > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++ > > I suggest we split this DTS into two parts: > 1. SOC (microchip-polarfire.dtsi) > 2. Board (microchip-icicle-kit-a000.dts)
I also doubt what is the correct board name. I suspect the -a000 comes from the SiFive board name convention, but does not apply to the Icicle Kit board.
@Cyril, please confirm.
> > This will be much cleaner and aligned with what is done > on other architectures. > > > 3 files changed, 316 insertions(+) > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts > >
Regards, Bin
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