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    Subject[PATCH 5.9 317/391] drm/amd/display: Fix incorrect backlight register offset for DCN
    Date
    From: David Galiffi <David.Galiffi@amd.com>

    commit 651111be24aa4c8b62c10f6fff51d9ad82411249 upstream.

    [Why]
    Typo in backlight refactor introduced wrong register offset.

    [How]
    SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

    Signed-off-by: David Galiffi <David.Galiffi@amd.com>
    Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
    Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: <stable@vger.kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
    +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
    @@ -54,7 +54,7 @@
    SR(BL_PWM_CNTL2), \
    SR(BL_PWM_PERIOD_CNTL), \
    SR(BL_PWM_GRP1_REG_LOCK), \
    - SR(BIOS_SCRATCH_2)
    + NBIO_SR(BIOS_SCRATCH_2)

    #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
    .field_name = reg_name ## __ ## field_name ## post_fix

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      Last update: 2020-11-03 22:49    [W:4.040 / U:0.276 seconds]
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