Messages in this thread Patch in this message |  | | From | Shenming Lu <> | Subject | [PATCH v2 1/2] irqchip/gic-v4.1: Reduce the delay time of the poll on the GICR_VPENDBASER.Dirty bit | Date | Sat, 28 Nov 2020 22:18:56 +0800 |
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The 10 delay_us of the poll on the GICR_VPENDBASER.Dirty bit is too high, which might greatly affect the total scheduling latency of a vCPU in our measurement. So we reduce it to 1 to lessen the impact.
Signed-off-by: Shenming Lu <lushenming@huawei.com> --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 0fec31931e11..22f427135c6b 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3809,7 +3809,7 @@ static void its_wait_vpt_parse_complete(void) WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER, val, !(val & GICR_VPENDBASER_Dirty), - 10, 500)); + 1, 500)); } static void its_vpe_schedule(struct its_vpe *vpe) -- 2.23.0
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