Messages in this thread |  | | Date | Fri, 27 Nov 2020 18:56:10 +0000 | From | Catalin Marinas <> | Subject | Re: [PATCH v1 1/3] irqchip/gic: enable irq target all |
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On Fri, Nov 27, 2020 at 06:11:01PM +0000, Marc Zyngier wrote: > On 2020-11-27 14:15, Hanks Chen wrote: > > Support for interrupt distribution design for SMP system solutions. > > As far as I know, we have been supporting interrupt distribution on > ARM SMP systems pretty well for the past... what... 15 years? > I'm sure Russell can dig out an ARM926 SMP system that even predates > that. > > > With this feature enabled ,the SPI interrupts would be routed to > > all the cores rather than boot core to achieve better > > load balance of interrupt handling. > > Please quantify this compared to the current distribution method. > > > That is, interrupts might be serviced simultaneously on different CPUs. > > They already can. What is new here? Or do you mean the *same* interrupt > being serviced by different CPUs *at the same time*? That'd be fun.
IIRC (it's been many years since I looked at the GIC), more than one CPU is woken and if they all read the INTACK, only one of them gets the actual IRQ number, the others see a spurious interrupt. I thought we decided that's not an efficient way to handle interrupts, so a software irqbalancer is better.
Has anything changed since then?
I'm also concerned that in a big.LITTLE system, you may see the big CPUs taking the interrupts all the time, which is nice for energy efficiency.
-- Catalin
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