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SubjectRe: boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets)
Date
Stefan,

On Wed, Nov 25 2020 at 14:41, Stefan Bühler wrote:
> On 11/25/20 12:54 PM, Thomas Gleixner wrote:
>> On Wed, Sep 16 2020 at 12:12, Stefan Bühler wrote:
>> Can you please provide the output of:
>>
>> for ID in 05:00.0 06:00.0 06:00.1 06:01.0 06:01.1; do lspci -s $ID -vvv; done
>
> See attachment.
>
> Also I boot the affected systems now with "pci=noioapicquirk", which
> "solves" the issue too (instead of patching the kernel).

Yes, it skips the quirks.

> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode])
> Physical Slot: 1
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0, Cache Line Size: 32 bytes
> Interrupt: pin A routed to IRQ 16
> NUMA node: 0
> Bus: primary=05, secondary=06, subordinate=06, sec-latency=64
> I/O behind bridge: 0000e000-0000efff
> Memory behind bridge: fb400000-fb4fffff
> Prefetchable memory behind bridge: fff00000-000fffff
> Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
> BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> Capabilities: <access denied>

Can you please run this as root so the Capabilities are accessible?

Thanks,

tglx

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