Messages in this thread | | | From | matthew.gerlach@linux ... | Subject | [PATCH v3 0/2] fpga: dfl: optional VSEC for start of dfl | Date | Tue, 24 Nov 2020 07:56:56 -0800 |
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From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
The start of a Device Feature List (DFL) is currently assumed to be at Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset adds support for the start one or more DFLs to be specified in a Vendor-Specific Capability (VSEC) structure in PCIe config space. If no such VSEC structure exists, then the start is assumed to be Bar0/Offset 0 for backward compatibility.
Matthew Gerlach (2): fpga: dfl: refactor cci_enumerate_feature_devs() fpga: dfl: look for vendor specific capability
Documentation/fpga/dfl.rst | 25 ++++++ drivers/fpga/dfl-pci.c | 169 +++++++++++++++++++++++++++++-------- 2 files changed, 159 insertions(+), 35 deletions(-)
-- 2.25.2
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