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Subject[PATCH 0/6] STM32 USBPHYC PLL management rework
Date
STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8
supplies. To ensure a good behavior of the PLL, during boot, runtime and
suspend/resume sequences, this series reworks its management to fix regulators
issues and improve PLL status reliability.

Amelie Delaunay (6):
dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node
phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation
phy: stm32: replace regulator_bulk* by multiple regulator_*
phy: stm32: ensure pll is disabled before phys creation
phy: stm32: ensure phy are no more active when removing the driver
phy: stm32: rework PLL Lock detection

.../bindings/phy/phy-stm32-usbphyc.yaml | 22 +-
drivers/phy/st/phy-stm32-usbphyc.c | 222 +++++++++++-------
2 files changed, 153 insertions(+), 91 deletions(-)

--
2.17.1

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