Messages in this thread | | | Date | Mon, 23 Nov 2020 15:10:49 +0000 | From | Russell King - ARM Linux admin <> | Subject | Re: [PATCH v1] net: mvpp2: divide fifo for dts-active ports only |
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Hi,
On Mon, Nov 23, 2020 at 04:52:40PM +0200, stefanc@marvell.com wrote: > From: Stefan Chulski <stefanc@marvell.com> > > Tx/Rx FIFO is a HW resource limited by total size, but shared > by all ports of same CP110 and impacting port-performance. > Do not divide the FIFO for ports which are not enabled in DTS, > so active ports could have more FIFO. > > The active port mapping should be done in probe before FIFO-init.
It would be nice to know what the effect is from this - is it a small or large boost in performance?
What is the effect when the ports on a CP110 are configured for 10G, 1G, and 2.5G in that order, as is the case on the Macchiatobin board?
Thanks.
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