Messages in this thread | | | Date | Fri, 20 Nov 2020 17:18:39 +0100 | From | Thierry Reding <> | Subject | Re: [PATCH] clk: tegra: Do not return 0 on failure |
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On Fri, Nov 20, 2020 at 05:16:56PM +0100, Thierry Reding wrote: > On Wed, Oct 28, 2020 at 05:48:20PM -0700, Nicolin Chen wrote: > > Return values from read_dt_param() will be either TRUE (1) or > > FALSE (0), while dfll_fetch_pwm_params() returns 0 on success > > or an ERR code on failure. > > > > So this patch fixes the bug of returning 0 on failure. > > > > Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control") > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > > --- > > drivers/clk/tegra/clk-dfll.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > Mike, Stephen, > > if you don't mind, I'll pick this up in the Tegra tree since there are a > few other Tegra clock patches on the list that may require coordination > inside the Tegra tree.
Also, I do plan on sending the collected set of patches to you for inclusion via PR at a later date, if that's okay with you.
Thierry [unhandled content-type:application/pgp-signature] | |