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    SubjectRe: [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift
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    On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong.li@sifive.com wrote:
    > The clk enable bit should be 31 instead of 24.
    >
    > Signed-off-by: Zong Li <zong.li@sifive.com>
    > Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
    > ---
    > drivers/clk/sifive/sifive-prci.h | 4 ++--
    > 1 file changed, 2 insertions(+), 2 deletions(-)
    >
    > diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
    > index 802fc8fb9c09..da7be9103d4d 100644
    > --- a/drivers/clk/sifive/sifive-prci.h
    > +++ b/drivers/clk/sifive/sifive-prci.h
    > @@ -59,7 +59,7 @@
    >
    > /* DDRPLLCFG1 */
    > #define PRCI_DDRPLLCFG1_OFFSET 0x10
    > -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
    > +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
    > #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
    >
    > /* GEMGXLPLLCFG0 */
    > @@ -81,7 +81,7 @@
    >
    > /* GEMGXLPLLCFG1 */
    > #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
    > -#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 24
    > +#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 31
    > #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
    >
    > /* CORECLKSEL */

    Section 7.3 of v1.0 of the FU540 manual says that bit 24 contains the PLL clock
    enable for both of these. I don't know if that's accurate, but if it is then I
    believe this would break the FU540. Don't have one to test on, though.

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