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    Subject[PATCH 5/8] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
    Date
    Add PCIe device tree node (both RC and EP) for the single PCIe
    instance present in j7200.

    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    ---
    arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 58 +++++++++++++++++++++++
    1 file changed, 58 insertions(+)

    diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
    index 7668404c178b..9892704d4b67 100644
    --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
    @@ -25,6 +25,14 @@
    #size-cells = <1>;
    ranges = <0x00 0x00 0x00100000 0x1c000>;

    + pcie1_ctrl: pcie-ctrl@4074 {
    + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
    + reg = <0x00004074 0x4>;
    + #address-cells = <1>;
    + #size-cells = <1>;
    + ranges = <0x4074 0x4074 0x4>;
    + };
    +
    serdes_ln_ctrl: serdes-ln-ctrl@4080 {
    compatible = "mmio-mux";
    #mux-control-cells = <1>;
    @@ -478,6 +486,56 @@
    };
    };

    + pcie1_rc: pcie@2910000 {
    + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
    + reg = <0x00 0x02910000 0x00 0x1000>,
    + <0x00 0x02917000 0x00 0x400>,
    + <0x00 0x0d800000 0x00 0x00800000>,
    + <0x00 0x18000000 0x00 0x00001000>;
    + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
    + interrupt-names = "link_state";
    + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
    + device_type = "pci";
    + ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
    + max-link-speed = <3>;
    + num-lanes = <4>;
    + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
    + clocks = <&k3_clks 240 6>;
    + clock-names = "fck";
    + #address-cells = <3>;
    + #size-cells = <2>;
    + bus-range = <0x0 0xf>;
    + cdns,max-outbound-regions = <32>;
    + cdns,no-bar-match-nbits = <64>;
    + vendor-id = /bits/ 16 <0x104c>;
    + device-id = /bits/ 16 <0xb00f>;
    + msi-map = <0x0 &gic_its 0x0 0x10000>;
    + dma-coherent;
    + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
    + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
    + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
    + };
    +
    + pcie1_ep: pcie-ep@2910000 {
    + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
    + reg = <0x00 0x02910000 0x00 0x1000>,
    + <0x00 0x02917000 0x00 0x400>,
    + <0x00 0x0d800000 0x00 0x00800000>,
    + <0x00 0x18000000 0x00 0x08000000>;
    + reg-names = "intd_cfg", "user_cfg", "reg", "mem";
    + interrupt-names = "link_state";
    + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
    + ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
    + max-link-speed = <3>;
    + num-lanes = <4>;
    + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
    + clocks = <&k3_clks 240 6>;
    + clock-names = "fck";
    + cdns,max-outbound-regions = <16>;
    + max-functions = /bits/ 8 <6>;
    + dma-coherent;
    + };
    +
    usbss0: cdns-usb@4104000 {
    compatible = "ti,j721e-usb";
    reg = <0x00 0x4104000 0x00 0x100>;
    --
    2.17.1
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