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Subject[PATCH 0/9] PHY: Enhance Sierra SERDES
Date
Hi Vinod,

This series enhances Sierra SERDES for two things
1) Skip configuring SERDES if it's already configured by bootloader
2) Model PLLs within SERDES as DT in order to use any of the external
clocks connected to the two external reference clock pins.

The DT binding in this series depends on
http://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com

Faiz Abbas (2):
phy: ti: j721e-wiz: Don't configure wiz if its already configured
phy: cadence: sierra: Don't configure if any plls are already locked

Kishon Vijay Abraham I (7):
dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within
SERDES
phy: ti: j721e-wiz: Get PHY properties only for "phy" subnode
phy: cadence: cadence-sierra: Create PHY only for "phy" sub-nodes
phy: cadence: Sierra: Fix PHY power_on sequence
phy: cadence: sierra: Model reference receiver as clocks (gate clocks)
phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux
clocks)
phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks

.../bindings/phy/phy-cadence-sierra.yaml | 89 +++-
drivers/phy/cadence/phy-cadence-sierra.c | 499 ++++++++++++++++--
drivers/phy/ti/phy-j721e-wiz.c | 39 +-
3 files changed, 565 insertions(+), 62 deletions(-)

--
2.17.1

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