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    Subject[Patch v2 5/6] dts: qcom: sdm845: Add dt entries to support crypto engine.
    Date
    Add crypto engine (CE) and CE BAM related nodes and definitions to
    "sdm845.dtsi".

    Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
    ---
    arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 ++++++++++++++++++++++++++++
    1 file changed, 30 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
    index 40e8c11f23ab..b5b2ea97681f 100644
    --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
    @@ -2138,6 +2138,36 @@ ufs_mem_phy_lanes: lanes@1d87400 {
    };
    };

    + cryptobam: dma@1dc4000 {
    + compatible = "qcom,bam-v1.7.0";
    + reg = <0 0x01dc4000 0 0x24000>;
    + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&rpmhcc RPMH_CE_CLK>;
    + clock-names = "bam_clk";
    + #dma-cells = <1>;
    + qcom,ee = <0>;
    + qcom,controlled-remotely = <1>;
    + iommus = <&apps_smmu 0x704 0x1>,
    + <&apps_smmu 0x706 0x1>,
    + <&apps_smmu 0x714 0x1>,
    + <&apps_smmu 0x716 0x1>;
    + };
    +
    + crypto: crypto@1dfa000 {
    + compatible = "qcom,crypto-v5.4";
    + reg = <0 0x01dfa000 0 0x6000>;
    + clocks = <&gcc GCC_CE1_AHB_CLK>,
    + <&gcc GCC_CE1_AHB_CLK>,
    + <&rpmhcc RPMH_CE_CLK>;
    + clock-names = "iface", "bus", "core";
    + dmas = <&cryptobam 6>, <&cryptobam 7>;
    + dma-names = "rx", "tx";
    + iommus = <&apps_smmu 0x704 0x1>,
    + <&apps_smmu 0x706 0x1>,
    + <&apps_smmu 0x714 0x1>,
    + <&apps_smmu 0x716 0x1>;
    + };
    +
    ipa: ipa@1e40000 {
    compatible = "qcom,sdm845-ipa";

    --
    2.25.1
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