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    Subject[PATCH 5.9 093/255] drm/amdgpu: perform srbm soft reset always on SDMA resume
    Date
    From: Evan Quan <evan.quan@amd.com>

    [ Upstream commit 253475c455eb5f8da34faa1af92709e7bb414624 ]

    This can address the random SDMA hang after pci config reset
    seen on Hawaii.

    Signed-off-by: Evan Quan <evan.quan@amd.com>
    Tested-by: Sandeep Raghuraman <sandy.8925@gmail.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 27 ++++++++++++---------------
    1 file changed, 12 insertions(+), 15 deletions(-)

    diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
    index 20f108818b2b9..a3c3fe96515f2 100644
    --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
    +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
    @@ -1071,22 +1071,19 @@ static int cik_sdma_soft_reset(void *handle)
    {
    u32 srbm_soft_reset = 0;
    struct amdgpu_device *adev = (struct amdgpu_device *)handle;
    - u32 tmp = RREG32(mmSRBM_STATUS2);
    + u32 tmp;

    - if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
    - /* sdma0 */
    - tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
    - tmp |= SDMA0_F32_CNTL__HALT_MASK;
    - WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
    - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
    - }
    - if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
    - /* sdma1 */
    - tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
    - tmp |= SDMA0_F32_CNTL__HALT_MASK;
    - WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
    - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
    - }
    + /* sdma0 */
    + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
    + tmp |= SDMA0_F32_CNTL__HALT_MASK;
    + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
    + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
    +
    + /* sdma1 */
    + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
    + tmp |= SDMA0_F32_CNTL__HALT_MASK;
    + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
    + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;

    if (srbm_soft_reset) {
    tmp = RREG32(mmSRBM_SOFT_RESET);
    --
    2.27.0


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