Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Mon, 16 Nov 2020 11:56:45 +0100 | Subject | Re: [PATCH v4] clk: renesas: r8a774c0: Add RPC clocks |
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On Mon, Nov 16, 2020 at 11:10 AM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR > driver. > > Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed > clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC), > parent and the divider is set based on the register value CPG_RPCCKCR[4:3] > which has been set prior to booting the kernel. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v3->v4 > * Dropped cross verification of clock source > * Changed DEF_FIXED_RPCSRC_E3 macro so that SoC specific div can be passed > which would make addition of D3 SoC easier > * Renamed CLK_TYPE_GEN3E3_RPCSRC to CLK_TYPE_GEN3_E3_RPCSRC > * Updated the commit message
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.11.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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