Messages in this thread | | | Date | Fri, 13 Nov 2020 08:57:41 -0400 | From | Jason Gunthorpe <> | Subject | Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection |
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On Fri, Nov 13, 2020 at 02:42:02AM +0000, Tian, Kevin wrote:
> CPUID#1_ECX is a x86 thing. Do we need to figure out probably_on_ > bare_metal for every architecture altogether, or is it OK to just > handle it for x86 arch at this stage? Based on previous discussions > ims is just one piece of multiple technologies to enable SIOV-like > scalability. Ideally arch-specific enablement beyond ims (e.g. the > IOMMU part) will be required for such scaled usage thus we > may just leave ims disabled for non-x86 and wait until that time to > figure out arch specific probably_on_bare_metal?
At the very least you need to ensure that pci_subdevice_msi_create_irq_domain() fails entirely on other architectures until they can sort out these sorts of issues..
Jason
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