lkml.org 
[lkml]   [2020]   [Nov]   [10]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v8 20/26] ARM: tegra: Add interconnect properties to Tegra20 device-tree
    Date
    Add interconnect properties to the Memory Controller, External Memory
    Controller and the Display Controller nodes in order to describe hardware
    interconnection.

    Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
    ---
    arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++++++++++++++-
    1 file changed, 25 insertions(+), 1 deletion(-)

    diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
    index 9347f7789245..2e1304493f7d 100644
    --- a/arch/arm/boot/dts/tegra20.dtsi
    +++ b/arch/arm/boot/dts/tegra20.dtsi
    @@ -111,6 +111,17 @@ dc@54200000 {

    nvidia,head = <0>;

    + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
    + <&mc TEGRA20_MC_DISPLAY0B &emc>,
    + <&mc TEGRA20_MC_DISPLAY1B &emc>,
    + <&mc TEGRA20_MC_DISPLAY0C &emc>,
    + <&mc TEGRA20_MC_DISPLAYHC &emc>;
    + interconnect-names = "wina",
    + "winb",
    + "winb-vfilter",
    + "winc",
    + "cursor";
    +
    rgb {
    status = "disabled";
    };
    @@ -128,6 +139,17 @@ dc@54240000 {

    nvidia,head = <1>;

    + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
    + <&mc TEGRA20_MC_DISPLAY0BB &emc>,
    + <&mc TEGRA20_MC_DISPLAY1BB &emc>,
    + <&mc TEGRA20_MC_DISPLAY0CB &emc>,
    + <&mc TEGRA20_MC_DISPLAYHCB &emc>;
    + interconnect-names = "wina",
    + "winb",
    + "winb-vfilter",
    + "winc",
    + "cursor";
    +
    rgb {
    status = "disabled";
    };
    @@ -630,15 +652,17 @@ mc: memory-controller@7000f000 {
    interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
    #reset-cells = <1>;
    #iommu-cells = <0>;
    + #interconnect-cells = <1>;
    };

    - memory-controller@7000f400 {
    + emc: memory-controller@7000f400 {
    compatible = "nvidia,tegra20-emc";
    reg = <0x7000f400 0x400>;
    interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&tegra_car TEGRA20_CLK_EMC>;
    #address-cells = <1>;
    #size-cells = <0>;
    + #interconnect-cells = <0>;
    };

    fuse@7000f800 {
    --
    2.29.2
    \
     
     \ /
      Last update: 2020-11-11 02:16    [W:4.350 / U:0.580 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site