Messages in this thread | | | Subject | Re: [PATCH v1 11/30] drm/tegra: dc: Support OPP and SoC core voltage scaling | From | Dmitry Osipenko <> | Date | Wed, 11 Nov 2020 00:17:30 +0300 |
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10.11.2020 23:29, Thierry Reding пишет: >> + >> + dc->opp_table = dev_pm_opp_get_opp_table(dc->dev); >> + if (IS_ERR(dc->opp_table)) >> + return dev_err_probe(dc->dev, PTR_ERR(dc->opp_table), >> + "failed to prepare OPP table\n"); >> + >> + if (of_machine_is_compatible("nvidia,tegra20")) >> + hw_version = BIT(tegra_sku_info.soc_process_id); >> + else >> + hw_version = BIT(tegra_sku_info.soc_speedo_id); >> + >> + hw_opp_table = dev_pm_opp_set_supported_hw(dc->dev, &hw_version, 1); >> + err = PTR_ERR_OR_ZERO(hw_opp_table); > What's the point of this? A more canonical version would be: > > if (IS_ERR(hw_opp_table)) { > err = PTR_ERR(hw_opp_table); > dev_err(dc->dev, ...); > goto put_table; > } > > That uses the same number of lines but is much easier to read, in my > opinion, because it is the canonical form. >
Your variant is much more difficult to read for me :/
I guess the only reason it could be "canonical" is because PTR_ERR_OR_ZERO was added not so long time ago.
But don't worry, this code will be moved out in a v2 and it won't use PTR_ERR_OR_ZERO.
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