Messages in this thread Patch in this message | | | Date | Mon, 05 Oct 2020 07:53:58 -0000 | From | "tip-bot2 for Kan Liang" <> | Subject | [tip: perf/core] perf/x86/intel: Check perf metrics feature for each CPU |
| |
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 80a5ce116fc084e8a25d5a936617699e2931b611 Gitweb: https://git.kernel.org/tip/80a5ce116fc084e8a25d5a936617699e2931b611 Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Thu, 01 Oct 2020 14:17:11 -07:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Sat, 03 Oct 2020 16:30:56 +02:00
perf/x86/intel: Check perf metrics feature for each CPU
It might be possible that different CPUs have different CPU metrics on a platform. In this case, writing the GLOBAL_CTRL_EN_PERF_METRICS bit to the GLOBAL_CTRL register of a CPU, which doesn't support the TopDown perf metrics feature, causes MSR access error.
Current TopDown perf metrics feature is enumerated using the boot CPU's PERF_CAPABILITIES MSR. The MSR only indicates the boot CPU supports this feature.
Check the PERF_CAPABILITIES MSR for each CPU. If any CPU doesn't support the perf metrics feature, disable the feature globally.
Fixes: 59a854e2f3b9 ("perf/x86/intel: Support TopDown metrics on Ice Lake") Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20201001211711.25708-1-kan.liang@linux.intel.com --- arch/x86/events/intel/core.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index bdf28d2..7186098 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4083,6 +4083,17 @@ static void intel_pmu_cpu_starting(int cpu) if (x86_pmu.counter_freezing) enable_counter_freeze(); + /* Disable perf metrics if any added CPU doesn't support it. */ + if (x86_pmu.intel_cap.perf_metrics) { + union perf_capabilities perf_cap; + + rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); + if (!perf_cap.perf_metrics) { + x86_pmu.intel_cap.perf_metrics = 0; + x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); + } + } + if (!cpuc->shared_regs) return;
| |