Messages in this thread Patch in this message | | | Date | Sun, 04 Oct 2020 22:49:55 +0200 | From | Paul Cercueil <> | Subject | Re: [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer |
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Hi,
Le mer. 23 sept. 2020 à 19:02, Jiaxun Yang <jiaxun.yang@flygoat.com> a écrit : > Loongson64C and Loongson64G have extimer feature, which is a > timer sharing Cause.TI with cevt-r4k (named intimer). > > To ensure the cevt-r4k's usability, we need to add a callback for > clock device to switch intimer. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/include/asm/cpu-features.h | 4 ++++ > arch/mips/include/asm/cpu.h | 1 + > arch/mips/kernel/cevt-r4k.c | 25 +++++++++++++++++++++++++ > arch/mips/kernel/cpu-probe.c | 6 +++++- > 4 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/cpu-features.h > b/arch/mips/include/asm/cpu-features.h > index 78cf7e300f12..aec458eee2a5 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -576,6 +576,10 @@ > # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) > #endif > > +#ifndef cpu_has_extimer > +# define cpu_has_extimer __opt(MIPS_CPU_EXTIMER) > +#endif > + > #ifdef CONFIG_SMP > /* > * Some systems share FTLB RAMs between threads within a core > (siblings in > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h > index 388a82f28a87..854e1b44254b 100644 > --- a/arch/mips/include/asm/cpu.h > +++ b/arch/mips/include/asm/cpu.h > @@ -429,6 +429,7 @@ enum cpu_type_enum { > #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support > MAC2008 Fused multiply-add instruction */ > #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity > exception */ > #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */ > +#define MIPS_CPU_EXTIMER BIT_ULL(63) /* CPU has External Timer > (Loongson) */ > > /* > * CPU ASE encodings > diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c > index 995ad9e69ded..fae49e9215b4 100644 > --- a/arch/mips/kernel/cevt-r4k.c > +++ b/arch/mips/kernel/cevt-r4k.c > @@ -15,6 +15,8 @@ > > #include <asm/time.h> > #include <asm/cevt-r4k.h> > +#include <asm/cpu-features.h> > +#include <asm/mipsregs.h> > > static int mips_next_event(unsigned long delta, > struct clock_event_device *evt) > @@ -294,6 +296,24 @@ core_initcall(r4k_register_cpufreq_notifier); > > #endif /* !CONFIG_CPU_FREQ */ > > +#ifdef CONFIG_CPU_LOONGSON64 > +static int c0_compare_int_enable(struct clock_event_device *cd) > +{ > + if (cpu_has_extimer) > + set_c0_config6(LOONGSON_CONF6_INTIMER); > + > + return 0; > +} > + > +static int c0_compare_int_disable(struct clock_event_device *cd) > +{ > + if (cpu_has_extimer) > + clear_c0_config6(LOONGSON_CONF6_INTIMER); > + > + return 0; > +} > +#endif
static int __maybe_unused c0_compare_int_enable(...) { ... }
without the #ifdef.
Or better, move these two to loongson64 board code, with "extern int c0_compare_int_enable" in a header somewhere.
> + > int r4k_clockevent_init(void) > { > unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; > @@ -329,6 +349,11 @@ int r4k_clockevent_init(void) > cd->set_next_event = mips_next_event; > cd->event_handler = mips_event_handler; > > +#ifdef CONFIG_CPU_LOONGSON64 > + cd->set_state_oneshot = c0_compare_int_enable; > + cd->set_state_shutdown = c0_compare_int_disable; > +#endif > +
if (IS_ENABLED(CONFIG_CPU_LOONGSON64)) { cd->set_state_oneshot = ...; }
Although I think this is still incorrect: here you check whether the kernel supports this CPU, instead of checking what CPU you're running on.
Cheers, -Paul
> clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, > 0x7fffffff); > if (cp0_timer_irq_installed) > diff --git a/arch/mips/kernel/cpu-probe.c > b/arch/mips/kernel/cpu-probe.c > index 6be23f205e74..4f1e9ef2644e 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -2030,6 +2030,9 @@ static inline void decode_cpucfg(struct > cpuinfo_mips *c) > if (cfg2 & LOONGSON_CFG2_LEXT2) > c->ases |= MIPS_ASE_LOONGSON_EXT2; > > + if (cfg2 & LOONGSON_CFG2_LLFTP) > + c->options |= MIPS_CPU_EXTIMER; > + > if (cfg2 & LOONGSON_CFG2_LSPW) { > c->options |= MIPS_CPU_LDPTE; > c->guest.options |= MIPS_CPU_LDPTE; > @@ -2088,7 +2091,8 @@ static inline void cpu_probe_loongson(struct > cpuinfo_mips *c, unsigned int cpu) > * Also some early Loongson-3A2000 had wrong TLB type in Config > * register, we correct it here. > */ > - c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; > + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE | > + MIPS_CPU_EXTIMER; > c->writecombine = _CACHE_UNCACHED_ACCELERATED; > c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | > MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); > -- > 2.28.0 >
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