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    Subject[PATCH 5.4 271/408] clk: mediatek: add UART0 clock support
    Date
    From: Hanks Chen <hanks.chen@mediatek.com>

    [ Upstream commit 804a892456b73604b7ecfb1b00a96a29f3d2aedf ]

    Add MT6779 UART0 clock support.

    Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
    Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
    Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
    Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/mediatek/clk-mt6779.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
    index 608a9a6621a37..00920182bbe63 100644
    --- a/drivers/clk/mediatek/clk-mt6779.c
    +++ b/drivers/clk/mediatek/clk-mt6779.c
    @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
    "pwm_sel", 19),
    GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
    "pwm_sel", 21),
    + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
    + "uart_sel", 22),
    GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
    "uart_sel", 23),
    GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
    --
    2.25.1


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