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    Subject[PATCH 5.9 684/757] usb: dwc3: Add splitdisable quirk for Hisilicon Kirin Soc
    Date
    From: Yu Chen <chenyu56@huawei.com>

    [ Upstream commit f580170f135af14e287560d94045624d4242d712 ]

    SPLIT_BOUNDARY_DISABLE should be set for DesignWare USB3 DRD Core
    of Hisilicon Kirin Soc when dwc3 core act as host.

    [mchehab: dropped a dev_dbg() as only traces are now allowwed on this driver]

    Signed-off-by: Yu Chen <chenyu56@huawei.com>
    Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
    Signed-off-by: Felipe Balbi <balbi@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/usb/dwc3/core.c | 25 +++++++++++++++++++++++++
    drivers/usb/dwc3/core.h | 7 +++++++
    2 files changed, 32 insertions(+)

    diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
    index c8e0ef2c1db33..2f9f4ad562d4e 100644
    --- a/drivers/usb/dwc3/core.c
    +++ b/drivers/usb/dwc3/core.c
    @@ -119,6 +119,7 @@ static void __dwc3_set_mode(struct work_struct *work)
    struct dwc3 *dwc = work_to_dwc(work);
    unsigned long flags;
    int ret;
    + u32 reg;

    if (dwc->dr_mode != USB_DR_MODE_OTG)
    return;
    @@ -172,6 +173,11 @@ static void __dwc3_set_mode(struct work_struct *work)
    otg_set_vbus(dwc->usb2_phy->otg, true);
    phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
    phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
    + if (dwc->dis_split_quirk) {
    + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
    + reg |= DWC3_GUCTL3_SPLITDISABLE;
    + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
    + }
    }
    break;
    case DWC3_GCTL_PRTCAP_DEVICE:
    @@ -1349,6 +1355,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
    dwc->dis_metastability_quirk = device_property_read_bool(dev,
    "snps,dis_metastability_quirk");

    + dwc->dis_split_quirk = device_property_read_bool(dev,
    + "snps,dis-split-quirk");
    +
    dwc->lpm_nyet_threshold = lpm_nyet_threshold;
    dwc->tx_de_emphasis = tx_de_emphasis;

    @@ -1866,10 +1875,26 @@ static int dwc3_resume(struct device *dev)

    return 0;
    }
    +
    +static void dwc3_complete(struct device *dev)
    +{
    + struct dwc3 *dwc = dev_get_drvdata(dev);
    + u32 reg;
    +
    + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
    + dwc->dis_split_quirk) {
    + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
    + reg |= DWC3_GUCTL3_SPLITDISABLE;
    + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
    + }
    +}
    +#else
    +#define dwc3_complete NULL
    #endif /* CONFIG_PM_SLEEP */

    static const struct dev_pm_ops dwc3_dev_pm_ops = {
    SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
    + .complete = dwc3_complete,
    SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
    dwc3_runtime_idle)
    };
    diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
    index 2f04b3e42bf1c..ba0f743f35528 100644
    --- a/drivers/usb/dwc3/core.h
    +++ b/drivers/usb/dwc3/core.h
    @@ -138,6 +138,7 @@
    #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))

    #define DWC3_GHWPARAMS8 0xc600
    +#define DWC3_GUCTL3 0xc60c
    #define DWC3_GFLADJ 0xc630

    /* Device Registers */
    @@ -380,6 +381,9 @@
    /* Global User Control Register 2 */
    #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)

    +/* Global User Control Register 3 */
    +#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
    +
    /* Device Configuration Register */
    #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
    #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
    @@ -1052,6 +1056,7 @@ struct dwc3_scratchpad_array {
    * 2 - No de-emphasis
    * 3 - Reserved
    * @dis_metastability_quirk: set to disable metastability quirk.
    + * @dis_split_quirk: set to disable split boundary.
    * @imod_interval: set the interrupt moderation interval in 250ns
    * increments or 0 to disable.
    */
    @@ -1245,6 +1250,8 @@ struct dwc3 {

    unsigned dis_metastability_quirk:1;

    + unsigned dis_split_quirk:1;
    +
    u16 imod_interval;
    };

    --
    2.25.1


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