Messages in this thread Patch in this message | | | From | Weiyi Lu <> | Subject | [PATCH v4 14/34] clk: mediatek: Add MT8192 camsys rawa clock support | Date | Thu, 22 Oct 2020 20:37:07 +0800 |
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Add MT8192 camsys rawa clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-cam_rawa.c | 59 ++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawa.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 0cb9f73..230e3f7 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -461,6 +461,12 @@ config COMMON_CLK_MT8192_CAMSYS help This driver supports MediaTek MT8192 camsys clocks. +config COMMON_CLK_MT8192_CAMSYS_RAWA + bool "Clock driver for MediaTek MT8192 camsys_rawa" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 camsys_rawa clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index f446834..cf1ec78 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -64,5 +64,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o +obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWA) += clk-mt8192-cam_rawa.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-cam_rawa.c b/drivers/clk/mediatek/clk-mt8192-cam_rawa.c new file mode 100644 index 0000000..02efd68 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-cam_rawa.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs cam_rawa_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM_RAWA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &cam_rawa_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate cam_rawa_clks[] = { + GATE_CAM_RAWA(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "cam_sel", 0), + GATE_CAM_RAWA(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "cam_sel", 1), + GATE_CAM_RAWA(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "cam_sel", 2), +}; + +static int clk_mt8192_cam_rawa_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(CLK_CAM_RAWA_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, cam_rawa_clks, ARRAY_SIZE(cam_rawa_clks), clk_data); + if (r) + return r; + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} + +static const struct of_device_id of_match_clk_mt8192_cam_rawa[] = { + { .compatible = "mediatek,mt8192-camsys_rawa", }, + {} +}; + +static struct platform_driver clk_mt8192_cam_rawa_drv = { + .probe = clk_mt8192_cam_rawa_probe, + .driver = { + .name = "clk-mt8192-cam_rawa", + .of_match_table = of_match_clk_mt8192_cam_rawa, + }, +}; + +builtin_platform_driver(clk_mt8192_cam_rawa_drv); -- 1.8.1.1.dirty | |