Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic | Date | Fri, 2 Oct 2020 07:50:38 +0000 |
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From: Bert Vermeulen > Sent: 01 October 2020 23:23 > > On 10/1/20 8:34 AM, Pratyush Yadav wrote: > > So using an address width of 4 here is not necessarily the right thing > > to do. This change would break SMPT parsing for all flashes that use > > 3-byte addressing by default because SMPT parsing can involve register > > reads/writes. One such device is the Cypress S28HS flash. In fact, this > > was what prompted me to write the patch [0]. > > > > Before that patch, how did MX25L25635F decide to use 4-byte addressing? > > The SoCs I'm dealing with have an SPI_ADDR_SEL pin, indicating whether it > should be in 3 or 4-byte mode. The vendor's hacked-up U-Boot sets the mode > accordingly, as does their BSP. It seems to me like a misfeature, and I want > to just ignore it and do reasonable JEDEC things, but I have the problem > that the flash chip can be in 4-byte mode by the time it gets to my spi-nor > driver.
If these are the devices I think they are, can't you read the non-volatile config word (bit 0) to find out whether the device expects a 3 or 4 byte address and how many 'idle' clocks there are before the read data?
A device that requires 3 bytes of address can be set to a read delay of 12 cycles (rather than the usual 10) so that 'hardware' reads (typically from address 0) can transparently support devices that require 3 or 4 bytes addresses.
David
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