Messages in this thread | | | Date | Sun, 18 Oct 2020 22:25:39 +0200 | From | Andrew Lunn <> | Subject | Re: [PATCH 2/2] net: dsa: mv88e6xxx: Support serdes ports on MV88E6097 |
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> I assume you're talking about the PHY Control Register 0 bit 11. If so > that's for the internal PHYs on ports 0-7. Ports 8, 9 and 10 don't have > PHYs.
Hi Chris
I have a datasheet for the 6122/6121, from some corner of the web, Part 3 of 3, Gigabit PHYs and SERDES.
http://www.image.micros.com.pl/_dane_techniczne_auto/ui88e6122b2lkj1i0.pdf
Section 5 of this document talks about the SERDES registers. Register 0 is Control, register 1 is Status - Fiber, register 2 and 3 are the usual ID, 4 is auto-net advertisement etc.
Where these registers appear in the address space is not clear from this document. It is normally in document part 2 of 3, which my searching of the web did not find.
Andrew
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